1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
In accordance with the recent growing demand for a higher integration level of a semiconductor device, copper has come to be more extensively used as a material for an interconnect, a plug, a pad and so on. Copper has lower electrical resistance and better electromigration resistance than aluminum, which has been conventionally employed.
However, along with a further progress in micronization of elements, electromigration (hereinafter referred to as “EM”) has once again become a problem to be eliminated, even with a copper interconnect. A copper layer constituting a copper interconnect, generally formed by plating, consists of a number of combined copper grains of a polycrystalline structure. When a voltage is applied to a copper interconnect having such structure, mass transfer of the copper grains takes place through the grain boundary, resulting in occurrence of EM. In a smaller width interconnect, the problem of EM due to the mass transfer through the grain boundary is more serious since size of a copper grain is also smaller. With an object to solve such problem of EM, various studies are being made focusing on techniques of mixing another metal in a copper interconnect.
For example, the Japanese Laid-Open Patent Application No.11-204524 discloses an interconnect composed of a copper alloy containing silver, niobium or Al2O3. Specifically, this application provides a method for forming a copper alloy layer wherein a copper alloy layer containing silver is deposited over a bottom of an interconnect trench by sputtering, on which layer a copper layer is deposited by CVD or plating and then heat treatment is performed so that the silver originally contained in the copper alloy diffuses throughout the copper layer. Also, another method is provided wherein after depositing a copper layer by CVD or plating a silver layer is deposited on the copper layer by electrolytic plating, and then heat treatment is performed so that the silver diffuses into the copper layer.
However it is difficult by a conventional method to diffuse a dissimilar metal such as silver throughout an entire interconnect. In order to diffuse a dissimilar metal throughout the entire interconnect it is necessary to raise a temperature or extend a duration time of the heat treatment, while the semiconductor device is prone to be damaged during such intensified heat treatment. Therefore it is difficult to maintain a stable quality level in the semiconductor device production. Also, when depositing a copper alloy layer by sputtering over a bottom of an interconnect trench, since the copper alloy layer cannot be formed in a sufficient thickness in case where a minute interconnect is to be constituted, a sufficient amount of the dissimilar metal for the entire interconnect cannot be provided. On the other hand, when depositing a dissimilar metal by plating, either the dissimilar metal or copper eludes during the plating process because of a deposition potential difference, therefore it is difficult to form a uniform copper alloy layer.
To further complicate the matter, occurrence of stress migration in a copper interconnect has lately become another major problem to be solved. FIG. 1 includes schematic cross-sectional views of a copper multilayer interconnect formed by Damascene method. An upper layer interconnect 121b is connected with a lower layer interconnect 121a, and the upper layer interconnect 121b consists of a connecting plug and an interconnect formed thereon. In such copper multilayer interconnect, a void 122 may appear at the interface of the lower layer interconnect 121a and the plug of the upper layer interconnect 121b owing to stress migration of the copper, resultantly causing disconnection between interconnects which lowers a yield of the semiconductor devices, or by which the semiconductor device becomes unstable after a certain period of use.
In FIG. 1a the void 122 is formed on the side of the upper layer interconnect 121b. In other words, the void is located where the connecting plug constituting the upper layer interconnect 121b is to be. By contrast, in FIG. 1b the void 122 is on an upper surface of the lower layer interconnect 121a. Such a void 122 is considered to be formed because of an internal stress in the copper interconnect caused by heat history etc. during manufacturing process of the semiconductor device. Referring to FIG. 1a, the void 122 is considered to be formed when “suction” of copper is caused in the upper layer interconnect 121b, and the copper migrates upward in the connecting plug. Referring to FIG. 1b, the void 122 is considered to be formed when the cupper migrates in horizontal direction within the lower layer interconnect 121a.
According to studies pursued by the present inventors, it has been proved that such a void is most prone to be formed at a temperature of 150° C. which is the actual processing temperature of a semiconductor device, for example in a bonding process, photoresist baking process, etc. Such a void often causes disconnection between interconnects, and as a result a yield of the semiconductor devices is lowered, or the semiconductor device becomes unstable after a certain period of use. It is critical to increase stress migration resistance at the interface of the interconnect and the connecting plug, i.e. at the surface of the interconnect in order to minimize the formation of such void. However the foregoing conventional technique of depositing a dissimilar metal on a bottom of an interconnect trench is not capable of diffusing the dissimilar metal as far as a surface of the interconnect, and consequently not effective in improving the stress migration resistance.
With an object to restrain an occurrence of the EM and the stress migration, it is essential to study on materials to be employed for constituting a metal region such as interconnect, along with studies on manufacturing process.
In view of the foregoing problems, it is an object of the present invention to increase EM and stress migration resistance of a semiconductor device having a metal region to thereby improve its reliability. Also, it is another object of the invention to provide a manufacturing process by which such semiconductor device can be produced at a stable quality level.